diff --git a/mesecons_fpga/init.lua b/mesecons_fpga/init.lua
index e79022f..8799c5f 100644
--- a/mesecons_fpga/init.lua
+++ b/mesecons_fpga/init.lua
@@ -1,4 +1,5 @@
 local S = minetest.get_translator("mesecons_fpga")
+local F = minetest.formspec_escape
 
 local plg = {}
 plg.rules = {}
@@ -129,13 +130,13 @@ plg.register_nodes({
 			dir = 1
 			if user and user:is_player() then
 				minetest.chat_send_player(user:get_player_name(),
-						"FPGA ports have been rotated clockwise.")
+						S("FPGA ports have been rotated clockwise."))
 			end
 		elseif mode == screwdriver.ROTATE_AXIS then -- counter-clockwise
 			dir = -1
 			if user and user:is_player() then
 				minetest.chat_send_player(user:get_player_name(),
-						"FPGA ports have been rotated counter-clockwise.")
+						S("FPGA ports have been rotated counter-clockwise."))
 			end
 		end
 
@@ -200,17 +201,17 @@ plg.to_formspec_string = function(is)
 		return s .. tostring(1 + mapping[val]) .. "]"
 	end
 	local s = "size[9,9]"..
-		"label[3.4,-0.15;FPGA gate configuration]"..
-		"button_exit[7,7.5;2,2.5;program;Program]"..
+		"label[3.4,-0.15;"..F(S("FPGA gate configuration")).."]"..
+		"button_exit[7,7.5;2,2.5;program;"..F(S("Program")).."]"..
 		"box[4.2,0.5;0.03,7;#ffffff]"..
-		"label[0.25,0.25;op. 1]"..
-		"label[1.0,0.25;gate type]"..
-		"label[2.125,0.25;op. 2]"..
-		"label[3.15,0.25;dest]"..
-		"label[4.5,0.25;op. 1]"..
-		"label[5.25,0.25;gate type]"..
-		"label[6.375,0.25;op. 2]"..
-		"label[7.4,0.25;dest]"
+		"label[0.25,0.25;"..F(S("op. 1")).."]"..
+		"label[1.0,0.25;"..F(S("gate type")).."]"..
+		"label[2.125,0.25;"..F(S("op. 2")).."]"..
+		"label[3.15,0.25;"..F(S("dest")).."]"..
+		"label[4.5,0.25;"..F(S("op. 1")).."]"..
+		"label[5.25,0.25;"..F(S("gate type")).."]"..
+		"label[6.375,0.25;"..F(S("op. 2")).."]"..
+		"label[7.4,0.25;"..F(S("dest")).."]"
 	local x = 1 - 0.75
 	local y = 1 - 0.25
 	for i = 1, 14 do
@@ -278,13 +279,13 @@ plg.update_formspec = function(pos, is)
 	local err = lcore.validate(is)
 	if err == nil then
 		meta:set_int("valid", 1)
-		meta:set_string("infotext", "FPGA (functional)")
+		meta:set_string("infotext", S("FPGA (functional)"))
 	else
 		meta:set_int("valid", 0)
-		meta:set_string("infotext", "FPGA")
+		meta:set_string("infotext", S("FPGA"))
 		local fmsg = minetest.colorize("#ff0000", minetest.formspec_escape(err.msg))
 		form = form .. plg.red_box_around(err.i) ..
-			"label[0.25,8.25;The gate configuration is erroneous in the marked area:]"..
+			"label[0.25,8.25;"..F(S("The gate configuration is erroneous in the marked area:")).."]"..
 			"label[0.25,8.5;" .. fmsg .. "]"
 	end
 
@@ -315,7 +316,7 @@ plg.update = function(pos)
 	elseif mesecon.do_overheat(pos) then
 		plg.setports(pos, false, false, false, false)
 		meta:set_int("valid", 0)
-		meta:set_string("infotext", "FPGA (overheated)")
+		meta:set_string("infotext", S("FPGA (overheated)"))
 		return
 	end
 
diff --git a/mesecons_fpga/logic.lua b/mesecons_fpga/logic.lua
index 3dca154..aad3d69 100644
--- a/mesecons_fpga/logic.lua
+++ b/mesecons_fpga/logic.lua
@@ -1,3 +1,5 @@
+local S = minetest.get_translator("mesecons_fpga")
+
 local lg = {}
 
 -- (de)serialize
@@ -111,34 +113,34 @@ lg.validate_single = function(t, i)
 	local elem = t[i]
 	-- check for completeness
 	if elem.action == nil then
-		return {i = i, msg = "Gate type required"}
+		return {i = i, msg = S("Gate type required")}
 	elseif elem.action == "not" or elem.action == "buf" then
 		if elem.op1 ~= nil or elem.op2 == nil or elem.dst == nil then
-			return {i = i, msg = "Second operand (only) and destination required"}
+			return {i = i, msg = S("Second operand (only) and destination required")}
 		end
 	else
 		if elem.op1 == nil or elem.op2 == nil or elem.dst == nil then
-			return {i = i, msg = "Operands and destination required"}
+			return {i = i, msg = S("Operands and destination required")}
 		end
 	end
 	-- check whether operands/destination are identical
 	if compare_op(elem.op1, elem.op2) then
-		return {i = i, msg = "Operands cannot be identical"}
+		return {i = i, msg = S("Operands cannot be identical")}
 	end
 	if compare_op(elem.op1, elem.dst, true) or compare_op(elem.op2, elem.dst, true) then
-		return {i = i, msg = "Destination and operands must be different"}
+		return {i = i, msg = S("Destination and operands must be different")}
 	end
 	-- check whether operands point to defined registers
 	if elem.op1 ~= nil and elem.op1.type == "reg"
 			and not is_reg_written_to(t, elem.op1.n, i) then
-		return {i = i, msg = "First operand is undefined register"}
+		return {i = i, msg = S("First operand is undefined register")}
 	end
 	if elem.op2.type == "reg" and not is_reg_written_to(t, elem.op2.n, i) then
-		return {i = i, msg = "Second operand is undefined register"}
+		return {i = i, msg = S("Second operand is undefined register")}
 	end
 	-- check whether destination points to undefined register
 	if elem.dst.type == "reg" and is_reg_written_to(t, elem.dst.n, i) then
-		return {i = i, msg = "Destination is already used register"}
+		return {i = i, msg = S("Destination is already used register")}
 	end
 
 	return nil
diff --git a/mesecons_fpga/tool.lua b/mesecons_fpga/tool.lua
index 26ab49e..a6a0e0e 100644
--- a/mesecons_fpga/tool.lua
+++ b/mesecons_fpga/tool.lua
@@ -1,8 +1,10 @@
+local S = minetest.get_translator("mesecons_fpga")
+
 return function(plg)
 
 
 minetest.register_tool("mesecons_fpga:programmer", {
-	description = "FPGA Programmer",
+	description = S("FPGA Programmer"),
 	inventory_image = "jeija_fpga_programmer.png",
 	stack_max = 1,
 	on_place = function(itemstack, placer, pointed_thing)
@@ -17,11 +19,11 @@ minetest.register_tool("mesecons_fpga:programmer", {
 
 		local meta = minetest.get_meta(pos)
 		if meta:get_string("instr") == "//////////////" then
-			minetest.chat_send_player(placer:get_player_name(), "This FPGA is unprogrammed.")
+			minetest.chat_send_player(placer:get_player_name(), S("This FPGA is unprogrammed."))
 			return itemstack
 		end
 		itemstack:set_metadata(meta:get_string("instr"))
-		minetest.chat_send_player(placer:get_player_name(), "FPGA gate configuration was successfully copied!")
+		minetest.chat_send_player(placer:get_player_name(), S("FPGA gate configuration was successfully copied!"))
 		
 		return itemstack
 	end,
@@ -37,14 +39,14 @@ minetest.register_tool("mesecons_fpga:programmer", {
 
 		local imeta = itemstack:get_metadata()
 		if imeta == "" then
-			minetest.chat_send_player(user:get_player_name(), "Use shift+right-click to copy a gate configuration first.")
+			minetest.chat_send_player(user:get_player_name(), S("Use shift+right-click to copy a gate configuration first."))
 			return itemstack
 		end
 
 		local meta = minetest.get_meta(pos)
 		meta:set_string("instr", imeta)
 		plg.update_formspec(pos, imeta)
-		minetest.chat_send_player(user:get_player_name(), "Gate configuration was successfully written to FPGA!")
+		minetest.chat_send_player(user:get_player_name(), S("Gate configuration was successfully written to FPGA!"))
 
 		return itemstack
 	end