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Add MT 5.0 translation support
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@ -1,3 +1,4 @@
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local S = minetest.get_translator("mesecons_fpga")
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local lg = {}
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@ -132,34 +133,34 @@ lg.validate_single = function(t, i)
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-- check for completeness
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if not gate_data then
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return {i = i, msg = "Gate type is required"}
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return {i = i, msg = S("Gate type is required")}
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elseif gate_data.unary then
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if elem.op1 ~= nil or elem.op2 == nil or elem.dst == nil then
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return {i = i, msg = "Second operand (only) and destination are required"}
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return {i = i, msg = S("Second operand (only) and destination are required")}
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end
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else
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if elem.op1 == nil or elem.op2 == nil or elem.dst == nil then
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return {i = i, msg = "Operands and destination are required"}
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return {i = i, msg = S("Operands and destination are required")}
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end
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end
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-- check whether operands/destination are identical
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if compare_op(elem.op1, elem.op2) then
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return {i = i, msg = "Operands cannot be identical"}
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return {i = i, msg = S("Operands cannot be identical")}
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end
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if compare_op(elem.op1, elem.dst, true) or compare_op(elem.op2, elem.dst, true) then
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return {i = i, msg = "Destination and operands must be different"}
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return {i = i, msg = S("Destination and operands must be different")}
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end
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-- check whether operands point to defined registers
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if elem.op1 ~= nil and elem.op1.type == "reg"
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and not is_reg_written_to(t, elem.op1.n, i) then
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return {i = i, msg = "First operand is undefined register"}
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return {i = i, msg = S("First operand is undefined register")}
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end
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if elem.op2.type == "reg" and not is_reg_written_to(t, elem.op2.n, i) then
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return {i = i, msg = "Second operand is undefined register"}
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return {i = i, msg = S("Second operand is undefined register")}
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end
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-- check whether destination points to undefined register
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if elem.dst.type == "reg" and is_reg_written_to(t, elem.dst.n, i) then
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return {i = i, msg = "Destination is already used register"}
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return {i = i, msg = S("Destination is already used register")}
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end
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return nil
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