mirror of
https://github.com/minetest-mods/mesecons.git
synced 2024-09-27 23:00:29 +02:00
Add FPGA strings for translation
This commit is contained in:
parent
0f729bca65
commit
17168f2e89
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@ -1,4 +1,5 @@
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local S = minetest.get_translator("mesecons_fpga")
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local S = minetest.get_translator("mesecons_fpga")
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local F = minetest.formspec_escape
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local plg = {}
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local plg = {}
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plg.rules = {}
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plg.rules = {}
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@ -129,13 +130,13 @@ plg.register_nodes({
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dir = 1
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dir = 1
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if user and user:is_player() then
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if user and user:is_player() then
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minetest.chat_send_player(user:get_player_name(),
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minetest.chat_send_player(user:get_player_name(),
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"FPGA ports have been rotated clockwise.")
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S("FPGA ports have been rotated clockwise."))
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end
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end
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elseif mode == screwdriver.ROTATE_AXIS then -- counter-clockwise
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elseif mode == screwdriver.ROTATE_AXIS then -- counter-clockwise
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dir = -1
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dir = -1
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if user and user:is_player() then
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if user and user:is_player() then
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minetest.chat_send_player(user:get_player_name(),
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minetest.chat_send_player(user:get_player_name(),
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"FPGA ports have been rotated counter-clockwise.")
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S("FPGA ports have been rotated counter-clockwise."))
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end
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end
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end
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end
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@ -200,17 +201,17 @@ plg.to_formspec_string = function(is)
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return s .. tostring(1 + mapping[val]) .. "]"
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return s .. tostring(1 + mapping[val]) .. "]"
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end
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end
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local s = "size[9,9]"..
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local s = "size[9,9]"..
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"label[3.4,-0.15;FPGA gate configuration]"..
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"label[3.4,-0.15;"..F(S("FPGA gate configuration")).."]"..
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"button_exit[7,7.5;2,2.5;program;Program]"..
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"button_exit[7,7.5;2,2.5;program;"..F(S("Program")).."]"..
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"box[4.2,0.5;0.03,7;#ffffff]"..
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"box[4.2,0.5;0.03,7;#ffffff]"..
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"label[0.25,0.25;op. 1]"..
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"label[0.25,0.25;"..F(S("op. 1")).."]"..
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"label[1.0,0.25;gate type]"..
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"label[1.0,0.25;"..F(S("gate type")).."]"..
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"label[2.125,0.25;op. 2]"..
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"label[2.125,0.25;"..F(S("op. 2")).."]"..
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"label[3.15,0.25;dest]"..
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"label[3.15,0.25;"..F(S("dest")).."]"..
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"label[4.5,0.25;op. 1]"..
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"label[4.5,0.25;"..F(S("op. 1")).."]"..
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"label[5.25,0.25;gate type]"..
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"label[5.25,0.25;"..F(S("gate type")).."]"..
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"label[6.375,0.25;op. 2]"..
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"label[6.375,0.25;"..F(S("op. 2")).."]"..
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"label[7.4,0.25;dest]"
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"label[7.4,0.25;"..F(S("dest")).."]"
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local x = 1 - 0.75
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local x = 1 - 0.75
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local y = 1 - 0.25
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local y = 1 - 0.25
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for i = 1, 14 do
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for i = 1, 14 do
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@ -278,13 +279,13 @@ plg.update_formspec = function(pos, is)
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local err = lcore.validate(is)
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local err = lcore.validate(is)
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if err == nil then
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if err == nil then
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meta:set_int("valid", 1)
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meta:set_int("valid", 1)
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meta:set_string("infotext", "FPGA (functional)")
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meta:set_string("infotext", S("FPGA (functional)"))
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else
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else
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meta:set_int("valid", 0)
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meta:set_int("valid", 0)
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meta:set_string("infotext", "FPGA")
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meta:set_string("infotext", S("FPGA"))
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local fmsg = minetest.colorize("#ff0000", minetest.formspec_escape(err.msg))
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local fmsg = minetest.colorize("#ff0000", minetest.formspec_escape(err.msg))
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form = form .. plg.red_box_around(err.i) ..
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form = form .. plg.red_box_around(err.i) ..
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"label[0.25,8.25;The gate configuration is erroneous in the marked area:]"..
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"label[0.25,8.25;"..F(S("The gate configuration is erroneous in the marked area:")).."]"..
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"label[0.25,8.5;" .. fmsg .. "]"
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"label[0.25,8.5;" .. fmsg .. "]"
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end
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end
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@ -315,7 +316,7 @@ plg.update = function(pos)
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elseif mesecon.do_overheat(pos) then
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elseif mesecon.do_overheat(pos) then
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plg.setports(pos, false, false, false, false)
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plg.setports(pos, false, false, false, false)
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meta:set_int("valid", 0)
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meta:set_int("valid", 0)
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meta:set_string("infotext", "FPGA (overheated)")
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meta:set_string("infotext", S("FPGA (overheated)"))
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return
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return
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end
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end
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@ -1,3 +1,5 @@
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local S = minetest.get_translator("mesecons_fpga")
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local lg = {}
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local lg = {}
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-- (de)serialize
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-- (de)serialize
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@ -111,34 +113,34 @@ lg.validate_single = function(t, i)
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local elem = t[i]
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local elem = t[i]
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-- check for completeness
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-- check for completeness
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if elem.action == nil then
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if elem.action == nil then
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return {i = i, msg = "Gate type required"}
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return {i = i, msg = S("Gate type required")}
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elseif elem.action == "not" or elem.action == "buf" then
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elseif elem.action == "not" or elem.action == "buf" then
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if elem.op1 ~= nil or elem.op2 == nil or elem.dst == nil then
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if elem.op1 ~= nil or elem.op2 == nil or elem.dst == nil then
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return {i = i, msg = "Second operand (only) and destination required"}
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return {i = i, msg = S("Second operand (only) and destination required")}
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end
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end
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else
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else
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if elem.op1 == nil or elem.op2 == nil or elem.dst == nil then
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if elem.op1 == nil or elem.op2 == nil or elem.dst == nil then
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return {i = i, msg = "Operands and destination required"}
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return {i = i, msg = S("Operands and destination required")}
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end
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end
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end
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end
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-- check whether operands/destination are identical
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-- check whether operands/destination are identical
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if compare_op(elem.op1, elem.op2) then
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if compare_op(elem.op1, elem.op2) then
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return {i = i, msg = "Operands cannot be identical"}
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return {i = i, msg = S("Operands cannot be identical")}
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end
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end
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if compare_op(elem.op1, elem.dst, true) or compare_op(elem.op2, elem.dst, true) then
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if compare_op(elem.op1, elem.dst, true) or compare_op(elem.op2, elem.dst, true) then
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return {i = i, msg = "Destination and operands must be different"}
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return {i = i, msg = S("Destination and operands must be different")}
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end
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end
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-- check whether operands point to defined registers
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-- check whether operands point to defined registers
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if elem.op1 ~= nil and elem.op1.type == "reg"
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if elem.op1 ~= nil and elem.op1.type == "reg"
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and not is_reg_written_to(t, elem.op1.n, i) then
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and not is_reg_written_to(t, elem.op1.n, i) then
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return {i = i, msg = "First operand is undefined register"}
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return {i = i, msg = S("First operand is undefined register")}
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end
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end
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if elem.op2.type == "reg" and not is_reg_written_to(t, elem.op2.n, i) then
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if elem.op2.type == "reg" and not is_reg_written_to(t, elem.op2.n, i) then
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return {i = i, msg = "Second operand is undefined register"}
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return {i = i, msg = S("Second operand is undefined register")}
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end
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end
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-- check whether destination points to undefined register
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-- check whether destination points to undefined register
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if elem.dst.type == "reg" and is_reg_written_to(t, elem.dst.n, i) then
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if elem.dst.type == "reg" and is_reg_written_to(t, elem.dst.n, i) then
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return {i = i, msg = "Destination is already used register"}
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return {i = i, msg = S("Destination is already used register")}
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end
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end
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return nil
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return nil
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@ -1,8 +1,10 @@
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local S = minetest.get_translator("mesecons_fpga")
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return function(plg)
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return function(plg)
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minetest.register_tool("mesecons_fpga:programmer", {
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minetest.register_tool("mesecons_fpga:programmer", {
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description = "FPGA Programmer",
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description = S("FPGA Programmer"),
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inventory_image = "jeija_fpga_programmer.png",
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inventory_image = "jeija_fpga_programmer.png",
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stack_max = 1,
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stack_max = 1,
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on_place = function(itemstack, placer, pointed_thing)
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on_place = function(itemstack, placer, pointed_thing)
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@ -17,11 +19,11 @@ minetest.register_tool("mesecons_fpga:programmer", {
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local meta = minetest.get_meta(pos)
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local meta = minetest.get_meta(pos)
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if meta:get_string("instr") == "//////////////" then
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if meta:get_string("instr") == "//////////////" then
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minetest.chat_send_player(placer:get_player_name(), "This FPGA is unprogrammed.")
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minetest.chat_send_player(placer:get_player_name(), S("This FPGA is unprogrammed."))
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return itemstack
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return itemstack
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end
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end
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itemstack:set_metadata(meta:get_string("instr"))
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itemstack:set_metadata(meta:get_string("instr"))
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minetest.chat_send_player(placer:get_player_name(), "FPGA gate configuration was successfully copied!")
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minetest.chat_send_player(placer:get_player_name(), S("FPGA gate configuration was successfully copied!"))
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return itemstack
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return itemstack
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end,
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end,
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@ -37,14 +39,14 @@ minetest.register_tool("mesecons_fpga:programmer", {
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local imeta = itemstack:get_metadata()
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local imeta = itemstack:get_metadata()
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if imeta == "" then
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if imeta == "" then
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minetest.chat_send_player(user:get_player_name(), "Use shift+right-click to copy a gate configuration first.")
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minetest.chat_send_player(user:get_player_name(), S("Use shift+right-click to copy a gate configuration first."))
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return itemstack
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return itemstack
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end
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end
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local meta = minetest.get_meta(pos)
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local meta = minetest.get_meta(pos)
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meta:set_string("instr", imeta)
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meta:set_string("instr", imeta)
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plg.update_formspec(pos, imeta)
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plg.update_formspec(pos, imeta)
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minetest.chat_send_player(user:get_player_name(), "Gate configuration was successfully written to FPGA!")
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minetest.chat_send_player(user:get_player_name(), S("Gate configuration was successfully written to FPGA!"))
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return itemstack
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return itemstack
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end
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end
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