Improve FPGA port double assignment test

2022-04-16 15:07:34 -04:00 · 2022-04-16 15:07:34 -04:00 · 4342e64e8c
parent 749f7b5267
commit 4342e64e8c
1 changed files with 1 additions and 1 deletions
--- a/mesecons_fpga/spec/logic_spec.lua
+++ b/mesecons_fpga/spec/logic_spec.lua
@ -127,7 +127,7 @@ describe("FPGA logic", function()
 	end)

 	it("allows double port assignment", function()
-		test_program({a = true}, {b = true}, {{"=", "A", "B"}, {"=", "A", "B"}})
+		test_program({a = true}, {b = true}, {{"NOT", "A", "B"}, {"=", "A", "B"}})
 	end)

 	it("allows assignment to port operand", function()